Sandeep Shukla

Photograph of Sandeep ShuklaOffice: 341 Durham
Mailing Address: 302 Whittemore (0111)
Virginia Tech
Blacksburg, VA 24061
Tel: (540) 231-2133
Fax: (540) 231-3362
vt.edu Email: shukla


Affiliated Research Group
FERMAT Lab

Personal website



Title: Associate Professor

Education:
Ph.D., State University of New York at Albany, 1997
M.S., State University of New York at Albany, 1995
B.E., Jadavpur University, Calcutta, India, 1991

Teaching Interests:
Formal methods, System level design for hardware, software, and embedded systems, Network application design, Formal verification, Stochastic methods in embedded systems design, Embedded software engineering, System synthesis

Research Interests:
Formal methods, System level design languages and frameworks, Component based and platform based design, System level power management, Formal verification and its use in system design, Concurrency analysis, Embedded systems design and co-design, Software engineering for embedded aystems, Distributed object technology and its application in embedded systems design, Networked embedded systems, Self-stabilization and fault-tolerant distributed systems


Textbooks Published


 

Ingredients for Successful System Level Design Methodology

Authors: Patel, Hiren D., Shukla, Sandeep Kumar

(Springer), 2008

 

SystemC Kernel Extensions for Heterogeneous System Modeling: A Framework for Multi-MoC Modeling & Simulation
Authors: Patel, Hiren D., Shukla, Sandeep Kumar
(Kluwer Academic (Springer) Publishers), 2004, E-Book


Formal Methods and Models for System Design: A System Level Perspective
Authors: Gupta, R.; Le Guernic, P.; Shukla, S.K.; Talpin, J.-P. (Eds.)
(Kluwer Academic (Springer) Publishers), 2004, E-Book


Nano, Quantum and Molecular Computing Implications to High Level Design and Validation
Authors: Shukla, Sandeep Kumar; Bahar, R. Iris (Eds.)
(Kluwer Academic (Springer) Publishers), 2004, E-Book